Simultaneous Switching Noise (SSN) is defined as a noise voltage induced onto a single victim Input/Output (I/O) pin of an electronic component due to the switching behavior of other aggressor I/O pins in the device. This noise is considered in the context of either an output I/O driver victim or an input I/O buffer victim.
The optimization of SSN in a Field Programmable Gate Array (FPGA) design is a multi-dimensional optimization problem. Current optimization techniques are manual and highly iterative. These iterations can take a prohibitively long time due to the nature of signoff SSN analysis tools. Additionally, the design process does not give the Computer Aided Design (CAD) tool enough information and flexibility to perform many of these optimizations without user intervention, thus increasing design time and less-than optimal quality of results.
It is in this context that embodiments of the invention arise.